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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
Rev. 02 -- 24 June 2010 Product data sheet
1. General description
The GreenChip III is the third generation of green Switched Mode Power Supply (SMPS) controller ICs. The TEA1752T and TEA1752LT combine a controller for Power Factor Correction (PFC) and a flyback controller. The high level of integration facilitates the design of a cost-effective power supply using a minimum number of external components. The special built-in green functions provide high efficiency at all power levels. This applies to quasi-resonant operation at high power levels, quasi-resonant operation with valley skipping and reduced frequency operation at lower power levels. At low power levels, the PFC switches off to maintain high efficiency. During low power conditions, the flyback controller switches to frequency reduction mode and limits the peak current to an adjustable minimum value. This will ensure high efficiency at low power and good standby power performance while minimizing audible noise from the transformer. The TEA1752(L)T is a MultiChip Module (MCM), containing two chips. The proprietary high voltage BCD800 process which enables direct start-up from the rectified universal mains voltage in an effective and green way and a low voltage Silicon-On Insulator (SOI) which provides accurate, high speed protection functions and control. The TEA1752(L)T enables highly efficient and reliable supplies with power requirements of up to 250 W to be designed easily and with a minimum number of external components.
2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller Universal mains supply operation (70 V (AC) to 276 V (AC)) Dual boost PFC with accurate maximum output voltage (NXP Semiconductors patented, US patent number: US7575280) High level of integration, resulting in a very low external component count and a cost-effective design Adjustable PFC switch-off delay
2.2 Green features
On-chip start-up current source
NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
2.3 PFC green features
Valley/zero voltage switching for minimum switching losses (NXP Semiconductors patented, US patent number: US6256210) Frequency limitation to reduce switching losses PFC is switched off when a low load is detected at the flyback output
2.4 Flyback green features
Valley switching for minimum switching losses (NXP Semiconductors patented, US patent number: US6256210) Frequency reduction with fixed minimum peak current at low power operation to maintain high-efficiency at low output power levels
2.5 Protection features
Safe restart mode for system fault conditions Continuous mode protection by means of demagnetization detection for both converters (NXP Semiconductors patented, patent number: US5032967) UnderVoltage Protection (UVP) (foldback during overload) Accurate OverVoltage Protection (OVP) for PFC Accurate, adjustable OverVoltage Protection (OVP) for flyback converter (NXP Semiconductors patented, patent number: US6542386) Mains voltage independent OverPower Protection (OPP) (NXP Semiconductors patented, patent number: US6542386) Open control loop protection for both converters. The open-loop protection on the flyback converter is latched on the TEA1752LT and safe restart on the TEA1752T IC overtemperature protection Low and adjustable OverCurrent Protection (OCP) trip level for both converters General purpose input for latched protection, e.g. to be used for system OverTemperature Protection (OTP)
3. Applications
All applications requiring efficient and cost-effective power supply solutions to 250 W. Notebook adapters in particular can benefit from the high level of integration
TEA1752T_LT
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 24 June 2010
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
4. Ordering information
Table 1. Ordering information Package Name TEA1752T TEA1752LT SO16 SO16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 SOT109-1 Type number
TEA1752T_LT
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Product data sheet
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
5. Block diagram
PFCDRIVER 12 PFC driver
1.12 V 3.5 V
FBDRIVER 13 flyback driver
80 A
PFC gate
driver
driver flyback gate external protection
5 LATCH
low Vin VINSENSE 7 boost latch reset clamp
1.25 V
1.25 V
protection MAXIMUM PFC protection protection enable PFC R Q S Q S enable flyback R frequency reduction low power PFC OSCILLATOR VCC good Vo start flyback low power delay external protection PFC clamp time-out external protection OTP OVP flyback latch reset time-out ton max VUVLO protection external protection Vstartup Vth(UVLO) ton(max) FLYBACK OSCILLATOR frequency reduction SMPS CONTROL start flyback start stop PFC OPP MINIMUM OCP clamp low power delay protection enable flyback Vo short VCC good charge VALLEY DETECT internal supply OVP flyback OPP OPP OVP COUNTER 4 FBAUX ZERO CURRENT SIGNAL flyback gate start flyback START SOFT flyback driver BLANK 10 FBSENSE time-out 2.5 V 3.5 V
PFCCOMP 6
30 A
VOSENSE 9
2.50 V 3.5 V 15 A 3.5 V
3.7 V
3 FBCTRL
PFC clamp
boost Vo OVP
low Vin PFC protection
Vo start flyback Vo short OCP
S (TEA1752LT only) S LATCHED S PROTECTION S R S (TEA1752T only) S SAFE RESTART R PROTECTION CHARGE CONTROL
PFCSENSE 11
500 mV
BLANK
PFC driver enable PFC
60 A 3 A
60 A
SOFT START SOFT STOP
start stop PFC
PFCAUX 8
VALLEY DETECT
TIMER 4 s ZERO CURRENT SIGNAL OTP charge Vstartup Vth(UVLO)
PFC gate TIMER 50 s
-100 mV
low power
DELAY 14 PFCTIMER
low power delay 16 HV 1 VCC
TEMPERATURE
OTP 2 GND
80 mV
014aaa742
Remark: TEA1752LT time-out is latched. TEA1752T time-out is safe restart.
Fig 1.
Block diagram
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
6. Pinning information
6.1 Pinning
VCC GND FBCTRL FBAUX LATCH PFCCOMP VINSENSE PFCAUX
1 2 3 4 TEA1752(L)T 5 6 7 8
014aaa741
16 HV 15 HVS 14 PFCTIMER 13 FBDRIVER 12 PFCDRIVER 11 PFCSENSE 10 FBSENSE 9 VOSENSE
Fig 2.
Pin configuration: TEA1752(L)T (SOT109-1)
6.2 Pin description
Table 2. Symbol VCC GND FBCTRL FBAUX LATCH PFCCOMP VINSENSE PFCAUX VOSENSE FBSENSE PFCSENSE PFCDRIVER FBDRIVER PFCTIMER HVS HV Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description supply voltage ground control input for flyback input from auxiliary winding for demagnetization timing and overvoltage protection for flyback general purpose protection input frequency compensation pin for PFC sense input for mains voltage input from auxiliary winding for demagnetization timing for PFC and valley sensing of the PFC part sense input for PFC output voltage programmable current sense input for flyback programmable current sense input for PFC gate driver output for PFC gate driver output for flyback delay timer pin for PFC on/off control high voltage safety spacer, not connected high voltage start-up and valley sensing of flyback part
TEA1752T_LT
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Product data sheet
Rev. 02 -- 24 June 2010
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
7. Functional description
7.1 General control
The TEA1752(L)T contains controllers for a power factor correction circuit and for a flyback circuit. A typical configuration is shown in Figure 3.
D1
S1
Cbus
CSS1
RSS1
D2 T2 COUT
RAUX1
RS1
RSENSE1 S2
PFCDRIVER PFCAUX 12 8 PFCCOMP
compensation
PFCSENSE 11 9
VOSENSE
HV 16
FBTIMER 13 10 FBSENSE
RS2
6
RSS2
VINSENSE
7
TEA1752(L)T
CSS2 RSENSE2 RAUX2
4 FBAUX 1 FBCTRL 3 2 GND
RLOOP
VCC LATCH
CVCC
14 PFCTIMER
5
CTIMEOUT 014aaa750
Fig 3.
Typical configuration
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially the capacitor on the VCC pin is charged from the high voltage mains via the HV pin. If VCC is lower than Vtrip, the charge current is low. This protects the IC if the VCC pin is shorted to ground. The charge current above Vtrip is increased until VCC reaches Vth(UVLO) to achieve a short start-up time. If VCC is between Vth(UVLO) and Vstartup, the charge current is low again, ensuring a low duty cycle during fault conditions. The control logic activates the internal circuitry and switches off the HV charge current when the voltage on pin VCC passes the Vstartup level. The LATCH pin current source is then activated and the soft start capacitors on pins PFCSENSE and FBSENSE are charged and the clamp circuit on pin PFCCOMP is activated. When the LATCH pin voltage exceeds Ven(LATCH), the PFCCOMP pin voltage exceeds Ven(PFCCOMP) and the soft start capacitor on pin PFCSENSE pin is charged, the PFC circuit is activated. The flyback
TEA1752T_LT All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 24 June 2010
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
converter is also activated (providing the soft start capacitor on the FBSENSE pin is charged). The flyback converter output voltage is then regulated to its nominal value. The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4. If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches Vth(UVLO), the LATCH pin output is deactivated and the charge current is switched on again. When the flyback converter is started, the voltage on pin FBCTRL is monitored. If the flyback converter output voltage does not reach its intended regulation level in a predefined time, the voltage on pin FBCTRL reaches the Vto(FBCTRL) level and an error is assumed. The TEA1752T then initiates a safe restart, while in the TEA1752LT the protection is latched. When one of the protection functions is activated, both converters stop switching and the VCC voltage drops to Vth(UVLO). A latched protection recharges the capacitor CVCC via the HV pin, but does not restart the converters. For a safe restart protection, the capacitor is recharged via the HV pin and the device restarts. See Figure 1. In the event of an overvoltage protection of the PFC circuit where VVOSENSE > Vovp(VOSENSE), the PFC controller stops switching until the VOSENSE pin voltage drops back below Vovp(VOSENSE). If a mains undervoltage is detected where VVINSENSE < Vstop(VINSENSE), the PFC controller stops switching until VVINSENSE > Vstart(VINSENSE). When the voltage on pin VCC drops below the undervoltage lockout level, both controllers stop switching and reenter the safe restart mode. In this mode the driver outputs are disabled and the VCC pin voltage is recharged via the HV pin.
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
IHV Vstartup VCC Vth(UVLO) Vtrip
Vstart(VINSENSE) VINSENSE
Ven(PFCCOMP) PFCCOMP
Ven(LA TCH) LATCH PROTECTION soft start PFCSENSE
PFCDRIVER soft start FBSENSE
FBDRIVER Vto(FBCTRL) FBCTRL
Vstart(fb) VOSENSE VO charging VCC capacitor
starting converters
normal operation
protection
restart
014aaa744
Fig 4.
Start-up sequence, normal operation and restart sequence
7.1.2 Supply management
All internal control voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. Internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit.
7.1.3 Latch input
Pin LATCH is a general purpose input pin, which can be used to switch off both converters. The pin sources a current IO(LATCH) (80 A typical). Switching off both converters is stopped as soon as the voltage on this pin drops below 1.25 V.
TEA1752T_LT
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Product data sheet
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged above 1.35 V (typical). No internal filtering is carried out on this pin. An internal zener clamp of 2.9 V (typical) protects this pin from excessive voltages.
7.1.4 Fast latch reset
In a typical application the mains supply can be interrupted briefly to reset the latched protection. The PFC bus capacitor, Cbus, does not need to discharge for this latched protection to reset. Typically the PFC bus capacitor, Cbus, must discharge for the VCC to drop to this reset level. When the latched protection is set, the VINSENSE clamping circuit is disabled. See Section 7.2.10. When the VINSENSE voltage drops below 0.75 V (typical) then increases to 0.87 V (typical), the latched protection is reset. The latched protection is also reset by removing the voltage on pins VCC and HV.
7.1.5 OverTemperature Protection (OTP)
Integrated overtemperature protection ensures the IC stops switching if the junction temperature exceeds the thermal temperature shutdown limit. Capacitor CVCC will not recharge from the HV mains while OTP is active. The OTP circuit is supplied from the HV pin if the VCC supply voltage is insufficient. OTP is a latched protection that can be reset either by removing the voltage on pins VCC and HV or by the fast latch reset function. See Section 7.1.4.
7.2 Power Factor Correction circuit (PFC)
The power factor correction circuit operates in quasi-resonant or discontinuous conduction mode with valley switching. The next primary stroke only starts when the previous secondary stroke has ended and the voltage across the PFC MOSFET has reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correction circuit is operated in ton control. The resulting mains harmonic reduction of a typical application is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer has been demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the voltage across the PFC MOSFET. The next stroke is started when the voltage across the PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic Interference (EMI) (valley switching). If no demagnetization signal is detected on the PFCAUX pin, the controller generates a Zero Current Signal (ZCS), 50 s (typical), after the last PFCGATE signal. If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal, 4 s (typical), after demagnetization was detected.
TEA1752T_LT
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Product data sheet
Rev. 02 -- 24 June 2010
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
It is advisable to add a 5 k series resistor to this pin to provide surge protection for the internal circuitry against events such as lightning surge. To prevent incorrect switching due to external disturbance, this resistor should be placed as close as possible to the IC on the printed-circuit board.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max limit, the system switches over to discontinuous conduction mode. The PFC MOSFET is then only switched on at a minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The mathematical equation for the transfer function of a power factor corrector contains the square of the mains input voltage. In a typical application this results in a low bandwidth for low mains input voltages, while at high mains input voltages the Mains Harmonic Reduction (MHR) requirements may be hard to meet. The TEA1752(L)T incorporates a correction circuit to compensate for the mains input voltage influence. The average input voltage is measured via the VINSENSE pin and this information is fed to an internal compensation circuit. With this compensation it is possible to keep the regulation loop bandwidth constant over the full mains input range, yielding a fast transient response on load steps, while still complying with class-D MHR requirements. In a typical application, the regulation loop bandwidth is set by a resistor and two capacitors on the PFCCOMP pin.
7.2.5 Soft start-up (pin PFCSENSE)
To prevent audible transformer noise at start-up or during hiccup, the transformer peak current is increased slowly by the soft start function. This can be achieved by inserting RSS1 and CSS1 between pin PFCSENSE and the current sense resistor, RSENSE1. An internal current source charges the capacitor to VPFCSENSE = Istart(soft)PFC x RSS1. The voltage is limited to Vstart(soft)PFC. The start level and time constant of the increasing primary current level can be adjusted externally by changing the values of RSS1 and CSS1. softstart = 3 x R SS1 x C SS1 The charging current Istart(soft)PFC flows if the voltage on pin PFCSENSE is lower than 0.5 V (typical). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current source limits current Istart(soft)PFC. When the PFC starts switching, the Istart(soft)PFC current source is switched off (see Figure 5). Resistor RSS1 and capacitor CSS1 are also used to prevent audible noise, when the PFC is switched off by performing a soft stop.
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
S1
Istart(soft)PFC 60 A
SOFT START SOFT STOP CONTROL
RSS1
11 PFCSENSE
0.5 V
OCP
CSS1 RSENSE1
014aaa756
Fig 5.
Soft start-up of PFC
7.2.6 Low power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback converter switches to frequency reduction mode. When the internal switching frequency limit of the flyback drops below 48 kHz (typical), the power factor correction circuit is switched off to maintain high efficiency. The switch-off can be delayed by connecting a capacitor to the PFCTIMER pin (see Section 7.2.7). During low power mode operation the PFCCOMP pin is clamped to a minimum voltage of 3.5 V (typical) and a maximum voltage of 3.7 V (typical). The lower clamp voltage limits the maximum power delivered when the PFC is switched on again. The upper clamp voltage ensures the PFC can return to its normal regulation point in a limited amount of time when returning from low power mode. The power factor correction circuit restores normal operation when the internal switching frequency limit of the flyback converter rises above 86 kHz (typical).
7.2.7 PFC off delay (pin PFCTIMER)
When the internal switching frequency limit of the flyback controller drops below 48 kHz (typical), the PFC is switched off. To prevent the PFC from switching off due to a fast changing load at the flyback output, the PFC switch-off can be delayed by connecting a capacitor to the PFCTIMER pin. When the flyback controller detects a low power, it enters frequency reduction mode and the IC outputs a 10 A (typical) current to the PFCTIMER pin. When the voltage on the PFCTIMER pin reaches 3.6 V (typical), the PFC is switched off by performing a soft stop. When the flyback controller part leaves the frequency reduction mode, a switch discharges the PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops below 1.27 V (typical), the PFC is switched on (see Figure 6).
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
10 A
3.6 V 1.27 V
low power
R S
Q
low power delay (PFC on)
14
PFCTIMER
014aaa740
Fig 6. PFC start/stop via PFCTIMER pin
7.2.8 Dual boost PFC
The PFC output voltage depends on the mains input voltage. The mains input voltage is measured via the VINSENSE pin. Current is sourced from the VOSENSE pin if the voltage on the VINSENSE pin drops below 2.2 V (typical). To ensure a stable switch-over, a 200 mV transition region is inserted around the 2.2 V, see Figure 7. For low VINSENSE input voltages, the output current is 15 A (typical). This output current, in combination with the resistors on the VOSENSE pin, sets a lower PFC output voltage level at low mains voltages. At high mains input voltages the current is switched to zero. The PFC output voltage will then be at its maximum. As this current is zero in this situation, it does not effect the accuracy of the PFC output voltage. For proper switch-off behavior, the VOSENSE current is switched to its maximum value, (15 A (typical)), as soon as the voltage on pin VOSENSE drops below 2.1 V (typical).
2.2 V
VVINSENSE
-15 A II(VOSENSE)
014aaa097
Fig 7.
Voltage to current transfer function for dual boost PFC
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is measured via the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the VINSENSE pin is continuously monitored. When the voltage on this pin drops below the Vstop(VINSENSE) level, PFC switching is stopped.
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
The voltage on pin VINSENSE is clamped to a minimum value, Vstart(VINSENSE) + Vpu(VINSENSE), for a fast restart when mains input voltage is restored after a mains dropout.
7.2.11 Overvoltage protection (VOSENSE pin)
An overvoltage protection circuit is incorporated to prevent output overvoltage during load steps and mains transients. When voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching of the power factor correction circuit is inhibited. Switching of the PFC recommences when the VOSENSE pin voltage drops back below the Vovp(VOSENSE) level. When the resistor between pin VOSENSE and ground is open, the overvoltage protection is also triggered.
7.2.12 PFC open-loop protection (VOSENSE pin)
The power factor correction circuit will not start switching until the voltage on the VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open-loop and VOSENSE short circuit situations.
7.2.13 Driver (pin PFCDRIVER)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically -500 mA and a current sink capability of typically 1.2 A. This enables fast turn-on and turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1752(L)T includes a controller for a flyback converter. The flyback converter operates in quasi-resonant or discontinuous conduction mode with valley switching. The auxiliary winding of the flyback transformer provides demagnetization detection and powers the IC after start-up.
7.3.1 Multimode operation
The TEA1752(L)T flyback controller can operate in several modes (see Figure 8).
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
flyback switching frequency 125 kHz 86 kHz frequency reduction PFC off 48 kHz discontinuous with valley switching PFC on
Ipmin adjust
quasi-resonant
output power
014aaa745
Fig 8.
Multimode operation flyback
At high output power the converter switches to quasi-resonant mode. The next converter stroke is started after demagnetization of the transformer current. In quasi-resonant mode switching losses are minimized as the converter only switches on when the voltage across the external MOSFET is at its minimum (valley switching, see Section 7.3.2). To prevent high frequency operation at lower loads, the quasi-resonant operation changes to discontinuous mode operation with valley skipping, in which the EMI switching frequency is limited to fsw(fb)max (125 kHz typical). Again, the external MOSFET is only switched on when the voltage across the MOSFET is at its minimum. At very low power and standby levels the frequency is reduced by a Voltage Controlled Oscillator (VCO). The minimum frequency can be reduced to zero. During frequency reduction mode the primary peak current is kept constant at a minimum adjustable level to control the PFC on-power and off-power levels. Ipmin in frequency reduction mode will generally be greater than Ipmax / 4, so a high efficiency at low loads is guaranteed. As the primary peak current is low in frequency reduction operation, no audible noise is noticeable at switching frequencies in the audible range. Valley switching is also active in this mode. In frequency reduction mode the PFC controller is switched off and the flyback maximum frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9 ). For stable on and off switching of the PFC, hysteresis has been added. At no load operation the switching frequency can be reduced to (almost) zero.
TEA1752T_LT
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
fsw(fb)max
flyback switching frequency
PFC off
PFC on discontinuous with valley switching
frequency reduction
quasi-resonant
1.5 V
VFBCTRL
014aaa746
Fig 9.
Frequency control of flyback part
7.3.2 Valley switching (HV pin)
Figure 10 shows that a new cycle starts when the external MOSFET is activated. After the on-time (determined by the FBSENSE voltage and the FBCTRL voltage), the MOSFET is switched off and the secondary stroke starts. After the secondary stroke, the drain voltage 1 shows an oscillation with a frequency of approximately -------------------------------------------------- where Lp is ( 2 x x ( Lp x Cd ) ) the primary self-inductance of the flyback transformer and Cd is the capacitance on the drain node. When the internal oscillator voltage is high again and the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal oscillator signal. Valley switching allows high frequency operation as capacitive switching losses are reduced (see Equation 1). High frequency operation makes small and cost-effective magnetics possible. P = 1 x C x V 2 x f -d 2 (1)
TEA1752T_LT
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
primary stroke
secondary stroke
secondary ringing
drain
valley
secondary stroke
(2)
(1)
oscillator
014aaa027
(1) Start of new cycle at lowest drain voltage. (2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter for its good line regulation. The primary current is sensed by the FBSENSE pin across external resistor RSENSE2 (see Figure 3) and compared with an internal control voltage. The internal control voltage is proportional to the FBCTRL pin voltage (see Figure 11). The FBSENSE pin outputs a current of 3 A (typical). This current runs through resistors RS2 and RSS2 from the FBSENSE pin to the sense resistor, RSENSE2 and creates an offset voltage (See Figure 3). With this offset voltage, the minimum peak current of the flyback can be adjusted. Adjusting the minimum peak current level, will change the frequency reduction slope (See Figure 8).
TEA1752T_LT
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Product data sheet
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
Vsense(fb)max
0.65 V FBSENSE offset voltage PFC off flyback frequency reduction flyback cycle skip mode 0.325 V PFC on SENSE resistor peak voltage flyback discontinuous or QR
FBSENSE peak voltage
1.5 V
2.0 V
VFBCTRL
014aaa747
Fig 11. Peak current control of flyback part
7.3.4 Demagnetization (FBAUX pin)
The system is always in quasi-resonant or discontinuous conduction mode. The internal oscillator does not start a new primary stroke until the previous secondary stroke has ended. Demagnetization features a cycle-by-cycle output short circuit protection by immediately lowering the frequency (longer off-time), thus reducing the power level. Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (2 s typical). This suppression may be necessary at low output voltages and at start-up and in applications where the transformer has a large leakage inductance. If pin FBAUX is open circuit or not connected, a fault condition is assumed and the converter stops operating immediately. Operation restarts as soon as the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal resistor (typical resistance is 3 k). As soon as the voltage on this pin rises above 2.5 V (typical), this connection is disabled. Above 2.5 V the pin is biased with a small current. When the voltage on this pin rises above 4.5 V (typical), a fault is assumed and switching is inhibited. In the TEA1752T a restart will then be made, while in the TEA1752LT the protection will be latched. When a small capacitor is connected to this pin, a time-out function can be created to protect against an open control loop situation. (see Figure 12 and Figure 13) The time-out function can be disabled by connecting a resistor (100 k) to ground on the FBCTRL pin. If the pin is shorted to ground, switching of the flyback controller is inhibited. In normal operating conditions, when the converter is regulating the output voltage, the voltage on the FBCTRL pin is between 1.4 V (typical) and 2.0 V (typical) from minimum to maximum output power.
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Product data sheet
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
2.5 V
3.5 V
30 A
4.5 V
3 k
time-out
FBCTRL
014aaa049
Fig 12. Time-out protection circuit
4.5 V 2.5 V
VFBCTRL
output voltage intended output voltage not reached within time-out time. restart intended output voltage reached within time-out time.
014aaa050
Fig 13. Time-out protection (signals), safe restart in the TEA1752T
4.5 V 2.5 V
VFBCTRL
output voltage intended output voltage not reached within time-out time. latched
014aaa298
Fig 14. Time-out protection (signals), latched in the TEA1752LT
7.3.6 Soft start-up (pin FBSENSE)
To prevent audible transformer noise during start-up, the transformer peak current is slowly increased by the soft start function. This can be achieved by inserting a resistor (RSS2) and a capacitor (CSS2) between pin 10 (FBSENSE) and the current sense resistor.
TEA1752T_LT
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
An internal current source charges the capacitor to V = Istart(soft)fb x RSS2, with a maximum of approximately 0.63 V. The start level and the time constant of the increasing primary current level can be externally adjusted by changing the values of RSS2 and CSS2. softstart = 3 x R SS2 x C SS2 The soft start current Istart(soft)fb is switched on when VCC reaches Vstartup. When the voltage on pin FBSENSE has reached 0.63 V the flyback converter starts switching. The charging current Istart(soft)PFC flows if voltage on pin FBSENSE is below approximately 0.63 V. If the voltage on pin FBSENSE exceeds 0.63 V, the soft start current source limits the current. Once the flyback converter has started, the soft start current source is switched off.
S2
3 A Istart(soft)fb 60 A SOFT START CONTROL
RSS2
10 FBSENSE ocp level
OCP
CSS2 RSENSE2
014aaa748
Fig 15. Soft start-up of flyback
7.3.7 Maximum on-time
The flyback controller limits the `on-time' of the external MOSFET to 40 s (typical). When the `on-time' is longer than 40 s, the IC stops switching and enters the safe restart mode.
7.3.8 Overvoltage protection (FBAUX pin)
An output overvoltage protection is implemented in the GreenChip III series. This operates for the TEA1752(L)T by sensing the auxiliary voltage via the current flowing into pin FBAUX during the secondary stroke. The auxiliary winding voltage is a well defined replica of the output voltage. Voltage spikes are averaged by an internal filter. If the output voltage exceeds the OVP trip level, an internal counter starts counting subsequent OVP events. The counter has been added to prevent incorrect OVP detection which might occur during ESD or lightning events. If the output voltage exceeds the OVP trip level a few times and then not again in a subsequent cycle, the internal counter counts down at twice the speed it uses when counting up. However, when typically eight cycles of subsequent OVP events are detected, the IC assumes a true OVP and the OVP circuit switches the power MOSFET off. As the protection is latched, the converter only restarts after the internal latch is reset. In a typical application the mains should be interrupted to reset the internal latch.
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GreenChip III SMPS control IC
The output voltage Vo(OVP) at which the OVP function trips, can be set by the demagnetization resistor, RFBAUX : Ns V o ( OVP ) = ----------- ( I ovp ( FBAUX ) x R FBAUX + V clamp ( FBAUX ) ) N aux where Ns is the number of secondary turns and Naux is the number of auxiliary turns of the transformer. The current Iovp(FBAUX) is internally trimmed. The value of RFBAUX can be adjusted to the turns ratio of the transformer, making an accurate OVP detection possible.
7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is accurately measured cycle-by-cycle using external sense resistor RSENSE2. The OCP circuit limits the voltage on pin FBSENSE to an internal level (see Section 7.3.3). The OCP detection is suppressed during the leading edge blanking period, tleb, to prevent false triggering caused by switch-on spikes.
tleb OCP level
VFBSENSE t
014aaa022
Fig 16. OCP leading edge blanking
7.3.10 Overpower protection
During the primary stroke of the flyback converter its input voltage is measured by sensing the current that is drawn from pin FBAUX. This information is used to adjust the peak drain current of the flyback converter measured via pin FBSENSE. The internal compensation is such that an almost input voltage independent maximum output power can be realized. The OPP curve is given in Figure 17.
TEA1752T_LT
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GreenChip III SMPS control IC
VFBSENSE (V) 0.65
0.46
-360
IFBAUX (A)
-100
0
014aaa749
Fig 17. Overpower protection curve
7.3.11 Driver (pin FBDRIVER)
The driver circuit to the gate of the external power MOSFET has a current sourcing capability of typically -500 mA and a current sink capability of typically 1.2 A. This enables fast turn-on and turn-off of the power MOSFET for efficient operation.
8. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Voltages VCC VLATCH VFBCTRL VPFCCOMP VVINSENSE VVOSENSE VPFCAUX VFBSENSE supply voltage voltage on pin LATCH voltage on pin FBCTRL voltage on pin PFCCOMP voltage on pin VINSENSE voltage on pin VOSENSE voltage on pin PFCAUX voltage on pin FBSENSE current limited current limited current limited -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -25 -0.4 -0.4 -0.4 -0.4 -3 -1 -1 -1 duty cycle < 10 % -0.8 +38 +5 +5 +5 +5 +5 +25 +5 +5 +5 +650 0 +1 +10 +10 +2 V V V V V V V V V V V mA mA mA mA A Parameter Conditions Min Max Unit
VPFCSENSE voltage on pin PFCSENSE VPFCTIMER voltage on pin PFCTIMER VHV Currents IFBCTRL IFBAUX IPFCSENSE IFBSENSE IFBDRIVER current on pin FBCTRL current on pin FBAUX current on pin PFCSENSE current on pin FBSENSE current on pin FBDRIVER voltage on pin HV
TEA1752T_LT
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GreenChip III SMPS control IC
Table 3. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol IHV General Ptot Tstg Tj ESD VESD electrostatic discharge voltage class 1 human body model pins 1 to 13 pin 16 (HV) machine model charged device model
[1] [2]
[1] [1] [2]
Parameter current on pin HV total power dissipation storage temperature junction temperature
Conditions duty cycle < 10 %
Min -0.8 -
Max +2 8 0.6 +150 +150
Unit A mA W C C
IPFCDRIVER current on pin PFCDRIVER
Tamb < 75 C
-55 -40
-
2000 1500 200 500
V V V V
Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 resistor.
9. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air; JEDEC test board in free air; JEDEC test board Typ 124 37 Unit K/W K/W
10. Characteristics
Table 5. Characteristics Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol IHV Parameter current on pin HV Conditions VHV > 80 V VCC < Vtrip; Vth(UVLO) < VCC < Vstartup Vtrip < VCC < Vth(UVLO) with auxiliary supply VBR Vtrip
TEA1752T_LT
Min
Typ
Max
Unit
Start-up current source (pin HV) 8 650 0.55
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1.0 5.4 20 0.65
40 0.75
mA mA A V V
breakdown voltage trip voltage
Supply voltage management (pin VCC)
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NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
Table 5. Characteristics ...continued Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Vstartup Vth(UVLO) Vstart(hys) Vhys Ich(low) Ich(high) ICC(oper) Parameter start-up voltage undervoltage lockout threshold voltage hysteresis of start voltage hysteresis voltage low charging current high charging current operating supply current during start-up phase Vstartup - Vth(UVLO) VHV > 80 V; VCC < Vtrip or Vth(UVLO) < VCC < Vstartup VHV > 80 V; Vtrip < VCC < Vth(UVLO) no load on pins FBDRIVER and PFCDRIVER Conditions Min 21 14 6.3 -1.2 -4.6 2.25 Typ 22 15 300 7 -1.0 -5.4 3 Max 23 16 7.7 -0.8 -6.3 3.75 Unit V V mV V mA mA mA
Input voltage sensing PFC (pin VINSENSE) Vstop(VINSENSE) Vstart(VINSENSE) Vpu(VINSENSE) Ipu(VINSENSE) stop voltage on pin VINSENSE start voltage on pin VINSENSE pull-up voltage difference on pin VINSENSE pull-up current on pin VINSENSE active after Vstop(VINSENSE) is detected active after Vstop(VINSENSE) is detected 0.86 1.11 -55 4.0 0.89 1.15 -100 -47 0.92 1.19 -40 V V mV A V
Vmvc(VINSENSE)max maximum mains voltage compensation voltage on pin VINSENSE Vflr Vflr(hys) II(VINSENSE) Vbst(dual) fast latch reset voltage hysteresis of fast latch reset voltage input current on pin VINSENSE VVINSENSE > Vstop(VINSENSE) after Vstart(VINSENSE) is detected dual boost voltage current switch-over point switch-over region Loop compensation PFC (pin PFCCOMP) gm IO(PFCCOMP) Ven(PFCCOMP) Vclamp(PFCCOMP) transconductance output current on pin PFCCOMP enable voltage on pin PFCCOMP clamp voltage on pin PFCCOMP zero on-time voltage on pin PFCCOMP maximum on-time voltage on pin PFCCOMP low power mode; PFC off; lower clamp voltage upper clamp voltage Vton(PFCCOMP)zero Vton(PFCCOMP)max
[1]
active after Vth(UVLO) is detected
5 60 33 -45 3.4 1.20
0.75 0.12 33 2.2 200 80 39 -39 3.5 3.5 3.7 3.5 1.25
100 100 45 -33 3.6 1.30
V V nA V mV A/V A A V V V V V
VVOSENSE to IO(PFCCOMP) VVOSENSE = 2.0 V VVOSENSE = 3.3 V
[1]
TEA1752T_LT
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GreenChip III SMPS control IC
Table 5. Characteristics ...continued Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol ton(PFC) Parameter PFC on-time Conditions VVINSENSE = 3.3 V; VPFCCOMP = Vton(PFCCOMP)max VVINSENSE = 0.9 V; VPFCCOMP = Vton(PFCCOMP)max Output voltage sensing PFC (pin VOSENSE) Vth(ol)(VOSENSE) Vreg(VOSENSE) Vovp(VOSENSE) Ibst(dual) open-loop threshold voltage on pin VOSENSE regulation voltage on pin VOSENSE overvoltage protection voltage on pin VOSENSE dual boost current VVINSENSE < Vbst(dual) or VVOSENSE < 2.1 V VVINSENSE > Vbst(dual) Overcurrent protection PFC (pin PFCSENSE) Vsense(PFC)max tleb(PFC) Iprot(PFCSENSE) maximum PFC sense voltage PFC leading edge blanking time protection current on pin PFCSENSE PFC soft start current PFC soft start voltage PFC soft stop voltage PFC soft start resistance maximum PFC switching frequency minimum PFC off-time PFC valley recognition voltage change with time PFC valley recognition time PFC valley recognition time-out time comparator threshold voltage on pin PFCAUX PFC demagnetization time-out time
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Min 3.6 30
Typ 4.5 40
Max 5.0 53
Unit s s
Pulse width modulator PFC
for IO(PFCCOMP) = 0
1.15
-
V
2.475 2.500 2.525 V 2.60 0.49 0.51 250 -50 2.63 -15 -30 0.52 0.54 310 2.67 0.55 0.57 370 -5 V A nA V V ns nA
V/t = 50 mV/s V/t = 200 mV/s
Soft start PFC (pin PFCSENSE) Istart(soft)PFC Vstart(soft)PFC Vstop(soft)PFC Rstart(soft)PFC Oscillator PFC fsw(PFC)max toff(PFC)min (V/t)vrec(PFC) tvrec(PFC) tto(vrec)PFC 0.8 VPFCAUX = 1 V peak-to-peak demagnetization to V/t = 0
[2] [3]
-75 enabling voltage disabling voltage 0.46 0.42 12
-60 0.50 0.45 250 1.1 4
-45 0.54 0.48 1.4 1.7 300 50 6
A V V k kHz s V/s ns ns s
Valley switching PFC (pin PFCAUX)
3
Demagnetization management PFC (pin PFCAUX) Vth(comp)PFCAUX tto(demag)PFC -150 40 -100 50 -50 60 mV s
TEA1752T_LT
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GreenChip III SMPS control IC
Table 5. Characteristics ...continued Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Iprot(PFCAUX) Parameter protection current on pin PFCAUX source current on pin PFCTIMER sink current on pin PFCTIMER start voltage on pin PFCTIMER stop voltage on pin PFCTIMER source current on pin PFCDRIVER sink current on pin PFCDRIVER maximum output voltage on pin PFCDRIVER overvoltage protection current on pin FBAUX number of overvoltage protection cycles comparator threshold voltage on pin FBAUX protection current on pin FBAUX clamp voltage on pin FBAUX transformer ringing suppression time minimum flyback on-time maximum flyback on-time maximum flyback switching frequency VCO start voltage on pin FBCTRL PFC switch-on flyback switching frequency PFC switch-off flyback switching frequency VCO voltage difference on pin FBCTRL
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Conditions VPFCAUX = 50 mV
Min -75
Typ -
Max -5
Unit nA
PFC off delay (pin PFCTIMER) Isource(PFCTIMER) Isink(PFCTIMER) Vstart(PFCTIMER) Vstop(PFCTIMER) Isrc(PFCDRIVER) Isink(PFCDRIVER) VO(PFCDRIVER)max VPFCDRIVER = 2 V VPFCDRIVER = 2 V VPFCDRIVER = 10 V -10 0.9 1.27 3.6 -0.5 0.7 1.2 11 12 A mA V V A A A V
Driver (pin PFCDRIVER)
Overvoltage protection flyback (pin FBAUX) Iovp(FBAUX) Ncy(ovp) 279 6 300 8 321 12 A
Demagnetization management flyback (pin FBAUX) Vth(comp)FBAUX Iprot(FBAUX) Vclamp(FBAUX) tsup(xfmr_ring) 60 VFBAUX = 50 mV IFBAUX = -100 A IFBAUX = 300 A -75 80 110 -5 mV nA
-0.85 -0.7 0.79 1.5 0.94 2
-0.55 V 1.09 2.5 V s
Pulse width modulator flyback ton(fb)min ton(fb)max Oscillator flyback fsw(fb)max Vstart(VCO)FBCTRL fsw(fb)swon(PFC) fsw(fb)swoff(PFC) VVCO(FBCTRL) 100 1.3 125 1.5 86 48 -0.2 150 1.7 kHz V kHz kHz V 32 tleb 40 48 ns s
TEA1752T_LT
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GreenChip III SMPS control IC
Table 5. Characteristics ...continued Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol VFBCTRL Vto(FBCTRL) Rint(FBCTRL) IO(FBCTRL) Ito(FBCTRL) Parameter voltage on pin FBCTRL time-out voltage on pin FBCTRL internal resistance on pin FBCTRL output current on pin FBCTRL time-out current on pin FBCTRL VFBCTRL = 0 V VFBCTRL = 2 V VFBCTRL = 2.6 V VFBCTRL = 4.1 V Conditions for maximum flyback peak current enable voltage trip voltage Min 1.85 4.2 -1.4 -0.6 -36 Typ 2.0 2.5 4.5 3 Max 2.15 4.8 Unit V V V k Peak current control flyback (pin FBCTRL)
-1.19 -0.93 mA -0.5 -30 -0.4 -24 mA A
-34.5 -28.5 -22.5 A -75
[4]
Valley switching flyback (pin HV) (V/t)vrec(fb) td(vrec-swon) flyback valley recognition voltage change with time valley recognition to switch-on delay time flyback soft start current flyback soft start voltage flyback soft start resistance maximum flyback sense voltage V/t = 50 mV/s V/t = 200 mV/s enable voltage 150 +75 V/s ns
-
Soft start flyback (pin FBSENSE) Istart(soft)fb Vstart(soft)fb Rstart(soft)fb Vsense(fb)max Vsense(fb)min tleb(fb) Iadj(FBSENSE) -75 0.55 16 0.61 0.64 255 peak current -3.2 -60 0.63 0.65 0.68 305 -3.0 -45 0.70 0.69 0.72 355 -2.8 A V k V V ns A
Overcurrent protection flyback (pin FBSENSE)
minimum flyback sense voltage V/t = 50 mV/s flyback leading edge blanking time adjust current on pin FBSENSE maximum flyback sense voltage
0.305 0.325 0.345 V
Overpower protection flyback (pin FBSENSE) Vsense(fb)max V/t = 50 mV/s IFBAUX = 80 A IFBAUX = 120 A IFBAUX = 240 A IFBAUX = 360 A Driver (pin FBDRIVER) Isrc(FBDRIVER) Isink(FBDRIVER) VO(FBDRIVER)(max) source current on pin FBDRIVER sink current on pin FBDRIVER maximum output voltage on pin FBDRIVER VFBDRIVER = 2 V VFBDRIVER = 2 V VFBDRIVER = 10 V -0.5 0.7 1.2 11 12 A A A V 0.61 0.57 0.47 0.41 0.65 0.62 0.52 0.46 0.69 0.67 0.57 0.51 V V V V
TEA1752T_LT
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GreenChip III SMPS control IC
Table 5. Characteristics ...continued Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Vprot(LATCH) IO(LATCH) Ven(LATCH) Vhys(LATCH) Voc(LATCH) Parameter protection voltage on pin LATCH output current on pin LATCH enable voltage on pin LATCH hysteresis voltage on pin LATCH open-circuit voltage on pin LATCH IC protection level temperature hysteresis of IC protection level temperature Vprot(LATCH) < VLATCH < Voc(LATCH) at start-up Ven(LATCH) - Vprot(LATCH) Conditions Min 1.23 -85 1.30 80 2.65 Typ 1.25 -80 1.35 100 2.9 Max 1.27 -75 1.40 140 3.15 Unit V A V mV V LATCH input (pin LATCH)
Temperature protection Tpl(IC) Tpl(IC)hys 130 140 10 150 C C
[1] [2] [3] [4]
For a typical application with a compensation network on pin PFCCOMP (see Figure 3). Minimum required voltage change time for valley recognition on pin PFCAUX. Minimum time required between demagnetization detection and V/t = 0 on pin PFCAUX. Guaranteed by design.
TEA1752T_LT
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GreenChip III SMPS control IC
11. Application information
A power supply with the TEA1752(L)T consists of a power factor correction circuit followed by a flyback converter (See Figure 18). Capacitor CVCC buffers the IC supply voltage, which is powered via the high voltage rectified mains supply during start-up and via the auxiliary winding of the flyback converter during operation. Sense resistors RSENSE1 and RSENSE2 convert the current through MOSFETs S1 and S2 into a voltage on pins PFCSENSE and FBSENSE. The values of RSENSE1 and RSENSE2 define the maximum primary peak current on MOSFETs S1 and S2. In the example shown in Figure 18, the LATCH pin is connected to a Negative Temperature Coefficient (NTC) resistor. When the resistance drops below V prot ( LATCH ) ------------------------------- = 15.6 k ( typical ) , the protection is activated. A capacitor CTIMEOUT is I O ( LATCH ) connected to the FBCTRL pin. Time-out protection is activated typically after 10 ms for a 120 nF capacitor. RLOOP is added so the time-out capacitor does not interfere with the normal regulation loop. RS1 and RS2 prevent the soft start capacitors from being charged during normal operation due to negative voltage spikes across the sense resistors. Resistor RAUX1 protects the IC from damage during events such as lightning strikes.
TEA1752T_LT
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TEA1752T; TEA1752LT
GreenChip III SMPS control IC
D1
S1
Cbus
CSS1
RSS1
D2 T2 COUT
RAUX1
RS1
RSENSE1 S2
PFCDRIVER PFCAUX 12 8 PFCCOMP
compensation
PFCSENSE 11 9
VOSENSE
HV 16
FBTIMER 13 10 FBSENSE
RS2
6
RSS2
VINSENSE
7
TEA1752(L)T
CSS2 RSENSE2 RAUX2
4 FBAUX 1 FBCTRL 3 2 GND
RLOOP
VCC LATCH
CVCC
14 PFCTIMER
5
CTIMEOUT 014aaa750
Fig 18. Typical application diagram TEA1752(L)T
TEA1752T_LT
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GreenChip III SMPS control IC
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D
E
A X
c y HE vMA
Z
16 9
Q A2 pin 1 index Lp
1 8
A1
(A 3)
A
L wM detail X
e
bp
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
o
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 19. Package outline SOT109-1 (SO16)
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GreenChip III SMPS control IC
13. Revision history
Table 6. Revision history Release date 20100624 Data sheet status Product data sheet Change notice Supersedes TEA1752T_LT_1 Document ID TEA1752T_LT v.2 Modifications
* * * * *
Template upgraded to Rev 2.12.0 including revised legal information. Text and drawings updated throughout entire data sheet. Figure 1 updated. Vstop(soft)PFC added in Table 5. Minimum junction temperature changed in Table 3. Objective data sheet -
TEA1752T_LT_1
20090213
TEA1752T_LT
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GreenChip III SMPS control IC
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
14.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
TEA1752T_LT
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 02 -- 24 June 2010
32 of 34
NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip -- is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TEA1752T_LT
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 24 June 2010
33 of 34
NXP Semiconductors
TEA1752T; TEA1752LT
GreenChip III SMPS control IC
16. Contents
1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 PFC green features . . . . . . . . . . . . . . . . . . . . . 2 Flyback green features . . . . . . . . . . . . . . . . . . . 2 Protection features . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 General control . . . . . . . . . . . . . . . . . . . . . . . . . 6 Start-up and UnderVoltage LockOut (UVLO) . . 6 Supply management. . . . . . . . . . . . . . . . . . . . . 8 Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 OverTemperature Protection (OTP) . . . . . . . . . 9 Power Factor Correction circuit (PFC) . . . . . . . 9 ton control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Valley switching and demagnetization (PFCAUX pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Frequency limitation . . . . . . . . . . . . . . . . . . . . 10 Mains voltage compensation (VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . 10 Soft start-up (pin PFCSENSE) . . . . . . . . . . . . 10 Low power mode . . . . . . . . . . . . . . . . . . . . . . 11 PFC off delay (pin PFCTIMER) . . . . . . . . . . . 11 Dual boost PFC . . . . . . . . . . . . . . . . . . . . . . . 12 Overcurrent protection (PFCSENSE pin) . . . . 12 Mains undervoltage lockout/brownout protection (VINSENSE pin) . . . . . . . . . . . . . . 12 Overvoltage protection (VOSENSE pin) . . . . . 13 PFC open-loop protection (VOSENSE pin) . . 13 Driver (pin PFCDRIVER) . . . . . . . . . . . . . . . . 13 Flyback controller . . . . . . . . . . . . . . . . . . . . . . 13 Multimode operation . . . . . . . . . . . . . . . . . . . . 13 Valley switching (HV pin) . . . . . . . . . . . . . . . . 15 Current mode control (FBSENSE pin) . . . . . . 16 Demagnetization (FBAUX pin) . . . . . . . . . . . . 17 Flyback control/time-out (FBCTRL pin) . . . . . 17 Soft start-up (pin FBSENSE) . . . . . . . . . . . . . 18 Maximum on-time . . . . . . . . . . . . . . . . . . . . . . 19 Overvoltage protection (FBAUX pin) . . . . . . . 19 Overcurrent protection (FBSENSE pin) . . . . . 20 7.3.10 7.3.11 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 Overpower protection. . . . . . . . . . . . . . . . . . . Driver (pin FBDRIVER) . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 21 21 22 22 28 30 31 32 32 32 32 33 33 34
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 June 2010 Document identifier: TEA1752T_LT

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